One type of flash memory cell is the so-called triple poly (3Poly) sidewall spacer split-gate flash memory cell. FIG. 5 shows a schematic cross-sectional view of a 3Poly sidewall spacer split-gate flash memory cell 500. The memory cell 500 includes a gate stack 523 including a floating gate (FG) 502 and a logic or control gate (CG) 503 arranged above the floating gate 502, and a select gate (SG) 504 that is configured as a sidewall spacer and laterally disposed from a sidewall of the gate stack 523. The gate stack 523 and the select gate 504 are arranged above a substrate 501, and the gates 502, 503, 504 may be electrically insulated from one another and from the substrate 501 by one or more electrically insulating layers, e.g. oxide layers (not shown). The gate stack 523 and the select gate 504 are arranged over a channel region 505, which is formed between a source region 506 and a drain region 507 in the substrate 501. The gates 502, 503 and 504 of the memory cell 500 are in each case made of polysilicon.
The polysilicon used for the floating gate (FG) may sometimes be referred to as Poly1, and the polysilicon used for the logic/control gate (CG) may sometimes be referred to as Poly2. The logic/control gate may sometimes be referred to as PC.
A conventional 3Poly sidewall spacer cell using Poly1 (for FG) and Poly2 (for PC) may include the use of two lithography masks. Furthermore, an additional Poly3 module may be used to form the spacer select gate (SG). This Poly3 module may include polysilicon deposition, use of a poly spacer (PS) lithography mask (1+ generation litho ahead), and a reactive ion etch (RIE) process for the spacer formation, wherein the RIE process may be highly selective to oxide in order to avoid poly stringers.
For example, a process for manufacturing the flash memory cell 500 shown in FIG. 5 may include forming the gate stack 523 (including the polysilicon floating and control gates 502, 503) over the substrate 501 and carry out a liner oxidation first. Then, a polysilicon deposition followed by a reactive ion etch (RIE) may be carried out to form gate spacers on both sides (i.e., the source side and the drain side) of the gate stack 523. Then, using the poly spacer (PS) mask to block the drain side spacer while exposing the source side spacer, a reactive ion etch (RIE) process may be carried out to remove the source side spacer.
It may be a difficult task to completely remove the source side spacer from the gate stack 523 by the RIE process due to the structure, which is far from ideally planar and homogenous. In particular, polysilicon near the gate edge along the active-STI fence (in other words, along a boundary between an active region and an STI region) may be hard to remove completely. As a consequence, thin polysilicon residues (also referred to as polysilicon stringers) may be left after the etch process, which may form an undesirable electrical connection between the gate stack and a source side contact formed at a later stage. In order to prevent possible electrically shorted adjacent cells along the bitline caused by polysilicon stringers, the source side spacer should be removed completely during the etch process. In addition, an advanced technology lithography mask (for example, a next-generation (1+ generation) lithography mask, in other words a mask of one lithography generation ahead) may be applied as the PS mask which may require a tight CD (critical dimension) overlay of ½ (one half) of the gate length mask features to be printed on the wafer (for example, the typical gate length may be 1 F, where F is the minimum feature size in a respective generation node). A CD of ½ F may cause alignment issues that may require a next-generation lithography mask. The use of such a next-generation lithography mask may lead to an increase in the processing costs of the memory cell. Furthermore, in order to achieve a perfect removal of the source side spacer, the PS mask may need very exact alignment. That is, a slight misalignment of the PS mask may already lead to an incomplete removal of the spacer and should thus be avoided. In addition to the use of a next-generation lithography PS mask, a RIE process that is highly selective to oxide material of the insulating layers in the gate stack may be applied to achieve a perfect removal of the source side spacer and thus avoid poly stringers.
The formation of the polysilicon sidewall spacer select gate in accordance with the process described above may thus need the development of a new process module (Poly3 module).